1. Field of the Invention
The present invention relates to tunneling barriers, charge storage layers and/or semiconductor structures including tunneling barriers and charge storage layers, and also to methods for manufacturing the same.
2. Description of the Related Art
In the related art, charge-based nonvolatile flash memory technology, the ratio between retention time tR and program/erase (P/E) time tPE is about 1012-1014. To realize this tremendous ratio, field asymmetric tunneling processes in the tunneling barrier have to be deliberately engineered between data retention and data P/E. The asymmetry in the related art flash memory cells can be provided by external P/E voltages.
For example, in NAND flash memory, the asymmetry between the Fowler-Nordheim tunneling under data P/E and the direct tunneling during data retention is exploited. However, this related art approach limits the scalability of the P/E voltage, which is quickly becoming the major scaling roadblock, considering power dissipation, cycling endurance, and peripheral circuitry design.